The present invention relates to a semiconductor device, and more particularly, to an internal voltage generating circuit for generating an internal voltage that is used in an internal operation of a semiconductor memory device, which is capable of maintaining an internal voltage at a stable level even when a level of an external power supply voltage changes unstably.
Most semiconductor devices, e.g., dynamic random access memory (DRAM), include an internal voltage generating circuit inside a chip to generate internal voltages necessary for operations of internal circuits. The internal voltage generating circuit is a circuit for generating internal voltages of various levels by using an external power supply voltage (VDD) and a ground voltage (VSS).
The generation of a plurality of internal voltages includes an operation of generating a reference voltage and an operation of charge-pumping or down-converting the generated reference voltage.
Examples of a representative internal voltage generated using the charge pumping operation include a high voltage (VPP) and a back bias voltage (VBB), and examples of a representative internal voltage generated using the down-converting operation include a core voltage (VCORE).
The high voltage (VPP) is a voltage higher than an external power supply voltage (VDD). Upon access to a memory cell, the high voltage (VPP) is applied to a word line connected to a gate of a cell transistor in order to prevent loss of cell data, which is caused by a threshold voltage (Vth) of the cell transistor.
The back bias voltage (VBB) is a voltage lower than an external ground voltage (VSS). The back bias voltage (VBB) reduces the variation of the threshold voltage (Vth) of the cell transistor, which is caused by a body effect, thereby improving the operation stability of the cell transistor and reducing a channel leakage current generated at the cell transistor.
The core voltage (VCORE) is a voltage lower than an external power supply voltage (VDD) and higher than a ground voltage (VSS). The core voltage (VCORE) reduces power that is necessary to maintain a voltage level of data stored in a memory cell, and is used for stable operation of the cell transistor.
The internal voltage generating circuit generating the internal voltages (VPP, VBB, VCORE) is designed to operate at a predetermined deviation value within an operating voltage region and an operating temperature range of the semiconductor memory device.
FIG. 1 is a block diagram of a conventional semiconductor memory device.
Referring to FIG. 1, the conventional semiconductor memory device includes an active signal generator 120 for generating an active signal ACT, a level of which is determined according to an operation of the semiconductor memory device, a bandgap reference voltage generator 140 for generating a reference voltage VREF maintaining a constant target level, regardless of variation of process, voltage and temperature (PVT) of the semiconductor memory device, and an internal voltage generator 100 for generating an internal voltage VINT having a predefined level, based on the target level of the reference voltage VREF, in response to the active signal ACT.
In addition, the internal voltage generator 100 includes an internal voltage detecting unit 102 and an internal voltage driving unit 104. The internal voltage detecting unit 102 detects a level of an internal voltage (VINT) terminal, based on the target level of the reference voltage VREF, to generate an internal voltage detection signal VINT_DET in response to the active signal ACT. The internal voltage driving unit 104 drives the internal voltage (VINT) terminal with a predefined driving ability in response to the internal voltage detection signal VINT_DET.
The internal voltage VINT generated through the above-described procedures is input to the internal circuit 160 and used to enable the internal circuit 160 to perform a predefined internal operation.
In the internal voltage generator 100, a detailed circuit of the internal voltage driving unit 104 may be changed according to the kinds of the generated internal voltage. For example, a circuit for the pumping voltage (VPP) generated by the charge pumping operation is different from a circuit for the core voltage (VCORE) generated by the down-converting operation. However, their generation principles are similar to each other. Therefore, the circuit for the core voltage (VCORE) generated by the down-converting operation, which is simpler in the circuit configuration, will be described below. That is, the internal voltage VINT refers to the core voltage VCORE in the following description.
FIG. 2 is a circuit diagram of the internal voltage generator of FIG. 1
Referring to FIG. 2, the internal voltage generator 100 for generating the internal voltage VINT includes the internal voltage detecting unit 102 and the internal voltage driving unit 104.
The internal voltage detecting unit 102 includes a voltage comparator 1022 and a voltage divider 1024. The voltage divider 1024 divides a level of the internal voltage (VINT) terminal at a predefined ratio to generate a divided voltage DIV_VOL. In response to the active signal ACT, the voltage comparator 1022 compares the reference voltage VREF corresponding to the target level with the divided voltage DIV_VOL and outputs the internal voltage detection signal VINT_DET according to the comparison result.
The voltage divider 1024 of the internal voltage detecting unit 102 includes a first resistor R1 and a second resistor R2 connected in series between the internal voltage (VINT) terminal and a ground voltage (VSS) terminal. The divided voltage DIV_VOL is output through a connection node DIN of the first resistor R1 and the second resistor R2.
The voltage comparator 1022 of the internal voltage detecting unit 102 includes a first NMOS transistor N1, a second NMOS transistor N2, a first PMOS transistor P1, a second PMOS transistor P2, and a third NMOS transistor N3. The first NMOS transistor N1 has a gate receiving the divided voltage DIV_VOL, and a drain and a source connected between a driving node ZN and a common node COMM. The first NMOS transistor N1 controls a current flowing between the driving node ZN and the common node COMM in response to the divided voltage DIV_VOL. The second NMOS transistor N2 has a gate receiving the reference voltage VREF corresponding to the target level, and a drain and a source connected between an output node OUN and the common node COMM. The second NMOS transistor N2 controls a current flowing between the output node OUN and the common node COMM in response to the reference voltage VREF. The first PMOS transistor P1 and the second PMOS transistor P2 are connected between the driving node ZN and the output node OUN in a current mirror configuration and equalizes the current flowing through the driving node ZN and the current flowing through the output node OUN. The third NMOS transistor N3 has a gate receiving the active signal ACT, and a drain and source connected between the common node COMM and the ground voltage (VSS) terminal. The third NMOS transistor N3 controls the electrical connection of the common node COMM and the ground voltage (VSS) terminal in response to the active signal ACT.
In addition, the internal voltage driving unit 104 includes a PMOS transistor P3 having a gate receiving the internal voltage detection signal VINT_DET, and a source and a drain connected between the power supply voltage (VDD) terminal and the internal voltage (VINT) terminal. The PMOS transistor P3 controls a current flowing from the power supply voltage (VDD) terminal and the internal voltage (VINT) terminal in response to the internal voltage detection signal VINT_DET.
The operation of generating the internal voltage VINT in the conventional semiconductor memory device will be described below.
When the activated active signal ACT is input from the active signal generator 120, the internal voltage generator 100 starts to operate. The bandgap reference voltage generator 140 must already start to operate to generate the reference voltage VREF corresponding to the target level.
When the internal voltage generator 100 starts to operate, the internal voltage detecting unit 102 detects if the level of the internal voltage (VINT) terminal is higher than the target level of the reference voltage VREF. At this point, when the level of the internal voltage (VINT) terminal is higher than the target level, the internal voltage (VINT) terminal need not be driven. Thus, the internal voltage detecting unit 102 outputs the deactivated internal voltage detection signal VINT_DET. When the level of the internal voltage (VINT) terminal is lower than the target level, the internal voltage (VINT) terminal must be driven. Thus, the internal voltage detecting unit 102 outputs the activated internal voltage detection signal VINT_DET.
When the deactivated internal voltage detection signal VINT_DET is applied, the internal voltage driving unit 104 performs no operations. On the contrary, when the activated internal voltage detection signal VINT_DET is applied, the internal voltage driving unit 104 performs the operation of driving the internal voltage VINT.
At this point, the internal voltage driving unit 104 drives the internal voltage VINT to the external power supply voltage VDD by using a driver having a predefined driving ability. That is, since the level of the internal voltage (VINT) terminal does not reach the target level, the level of the internal voltage (VINT) terminal is increased by applying the external power supply voltage VDD higher than the target level to the internal voltage (VINT) terminal.
In this way, when the internal voltage driving unit 104 operates to increase the level of the internal voltage (VINT) terminal above the target level, the internal voltage detecting unit 102 detects the increased level of the internal voltage (VINT) terminal and stops the operation of the internal voltage driving unit 104.
By repeating the above-described operations, the internal voltage generator 100 operates such that the level of the internal voltage (VINT) terminal is always maintained at the target level in the activation period of the active signal ACT.
If the level of the external power supply voltage VDD changes due to the PVT variation of the semiconductor memory device, the internal voltage driving unit 104 of the internal voltage generator 100 operates as described below.
FIG. 3 is a waveform diagram of the internal voltage during the operation of generating the internal voltage in the conventional semiconductor memory device of FIG. 1.
Referring to FIG. 3, at a timing {circle around (1)} where the internal voltage driving unit 104 starts to operate, the internal circuit 160 uses the internal voltage VINT in operation so that the level of the internal voltage (VINT) terminal becomes lower than the target level. In addition, since the timing {circle around (1)} is a timing where the operation of the internal circuit 160 is not finished, it is expected that the level of the internal voltage (VINT) terminal will continuously fall.
Therefore, the internal voltage driving unit 104 must prevent the level of the internal voltage (VINT) terminal from being further lowered at a timing {circle around (2)} where the operation of the internal circuit 160 is not finished, and increase the level of the internal voltage (VINT) terminal at a timing {circle around (3)} where the operation of the internal circuit 160 is finished, so that the level of the internal voltage (VINT) terminal can maintain the voltage level corresponding to the target level.
When the level of the external power supply voltage VDD is maintained at the predefined level, the predefined driving ability of the internal voltage driving unit 106 is enough to drive the internal voltage (VINT) terminal. Thus, the internal voltage driving unit 106 may operate to prevent the level of the internal voltage (VINT) terminal from falling below an allowable lower limit at the timing {circle around (2)}, that is, before the operation of the internal circuit 160 is finished. Also, the internal voltage driving unit 106 may operate to increase the level of the internal voltage (VINT) terminal in a relatively short time at the timing {circle around (3)} where the operation of the internal circuit 160 is finished, so that the level of the internal voltage (VINT) terminal can maintain the level corresponding target level.
However, when the level of the external power supply voltage VDD is lower than the predefined level, the predefined driving ability of the internal voltage driving unit 106 is not enough to drive the internal voltage (VINT) terminal. Thus, even though the internal voltage driving unit 106 operates, the driving ability to increase the level of the internal voltage VINT is deficient and the level of the internal voltage (VINT) terminal falls relatively much more at the timing {circle around (2)}, that is, before the operation of the internal circuit 160 is finished. Hence, if the level of the internal voltage (VINT) terminal falls below the allowable lower limit, the normal data input/output operations are disturbed and the operation of the semiconductor memory device becomes unstable.
Furthermore, at the timing {circle around (3)} where the operation of the internal circuit 160 is finished, a relatively long time is taken to increase the level of the internal voltage (VINT) terminal to the target level.